About me
My name is Jiteshri Dasari. I am a third year PhD student in the VLSI CAD Lab at UMass Amherst, advised by Prof. Maciej Ciesielski.
My Research interests are in Formal Verification of arithmetic circuits and logic synthesis.
Check out my Research publications here
Prior to starting my PhD journey, I worked as a Senior RTL Engineer at Intel and Applications Engineer at Synopsys
I earned my Master's Degree in Electrical and Computer Engineering also from UMass Amherst in 2018.
During my spare time, I enjoy sketching, painting, traveling and enjoying new foods.
Exciting updates
- Started my Summer'23 internship at Synopsys in the Formality R&D team
- I am presenting our paper on 'Formal Verification of Restoring Dividers made Fast and Simple' at DAC'23
- Awarded DAC Young Fellows travel grant for DAC'23
- Awarded the Grace Hopper Scholarship for vGHC'22
- Summer'22 internship at Synopsys in the Formality R&D team
- Paper accepted at DDECS'22
- Started my PhD Journey in Fall'21 :)
Resume
A PDF version of my Resume can be found here
Contact
I can be reached at:
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